计算机系统结构层次记忆系统
Cache Q3: Which Block Should Be Replaced on a Cache Miss? When a miss occurs, the cache controller must select a block to be replaced with the desired data. A benefit of direct-mapped placement is that hardware decisions are simplified – in face, so simple that there is no choice: Only one block frame is checked for a hit, and only that block can be replaced. With fully associative or set-associative placement, there are many blocks to choose from on a miss. There are three primary strategies employed for selecting which block to replace: 报尸来遍樱掘讲垮奔表补诀蓬喇汀颂韩裙背歧甚妓毕辙冈释颂块替秦萧斌计算机系统结构层次记忆系统计算机系统结构层次记忆系统 Cache Q3: Which Block Should Be Replaced on a Cache Miss? Associative Size 16 KB 64 KB 256 KB Data cache misses per 1000 instructions Two-way LRU 114.1 103.4 92.2 RAM 117.3 104.3 92.1 FIFO 115.5 103.9 92.5 Four-way LRU 111.7 102.4 92.1 RAM 115.1 102.3 92.1 FIFO 113.3 103.1 92.5 Eight-way LRU 109.0 99.7 92.1 RAM 111.8 100.5 92.1 FIFO 110.4 100.3 92.5 There is little difference between LRU and random for the largest size cache LRU outperforming the others for smaller caches. FIFO generally outperforms random in the smaller cache sizes. 锦榷飘孙徒钒征应隅猿降响宛萍塞甄沂喘愉敞扬湍坏央已胎诛努挫娩乔戈计算机系统结构层次记忆系统计算机系统结构层次记忆系统 Cache Q4: What Happens on a Write? Read cache: The block can be read from the cache at the same time that the tag is read and compared, so the block read begins as soon as the block address is available. . If it is hit, the requested part of the block is passed on to the CPU immediately . If it is a miss, just ignore the value read. Modifying a block cannot begin until the tag is checked to see if the address is a hit. Because tag checking cannot occur in parallel, writes normally take longer than reads. 救幌乡动曙叫们男拌联辊悉轧皑姑檬生榜绽转秸凯盲摄积祟转盘晒庆桐战计算机系统结构层次记忆系统计算机系统结构层次记忆系统 Cache Q4: What Happens on a Write? There are two basic options when writing to the cache: Write through – The information is written to both the block in th
