实验目的
帮助学生理解现代时序系统中硬布线控制器设计的基本原理,学生能设计硬布线控制器核心部件状态机模块。
实验步骤:
利用数字逻辑电路相关知识设计现代时序硬布线核心部件状态机模块,实际状态机如下图: 按状态图填写5号excel表,自动生成次态逻辑表达式后,即可在logisim中自动生成该电路。 电路完成图:电路引脚
测试用例:
测试:
预期输出:Cnt SLW SW BEQ SLT ADDI NS0000000000101010000002000000303031000004040301000090503001000e060300010130703000011608040000005090500000060a0600000070b0700000080c0800000000d09000000a0e0a000000b0f0b000000c100c000000d110d0000000120e000000f130f0000000140f000001015100000011161100000121712000000018130000014191400000151a1500000001b1600000171c1700000181d180000000实际输出:Cnt SLW SW BEQ SLT ADDI NS0000000000101010000002000000303031000004040301000090503001000e060300010130703000011608040000005090500000060a0600000070b0700000080c0800000000d09000000a0e0a000000b0f0b000000c100c000000d110d0000000120e000000f130f0000000140f000001015100000011161100000121712000000018130000014191400000151a1500000001b1600000171c1700000181d180000000