STM32时钟系统(2)-时钟系统常用寄存器和库函数
STM32时钟系统
官方文档说明：
Three different clock sources can be used to drive the system clock (SYSCLK):
• HSI oscillator clock
• HSE oscillator clock
• PLL clock
The devices have the following two secondary clock sources:
• 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop/Standby mode.
• 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
大概意思：
SYSCLK系统时钟的来源有三个：
1.HSI oscillator clock (High Speed Internel)
2.HSE oscillator clock(High Speed External)
3.PLL clock(这个也是来自于HSE oscillator clock)
辅助时钟源有两个(LSI RC和LSE crystal)，晶振频率是40kHz和32.786kHz,
可以独立的打开和关闭，优化系统功耗。
HSE Clock
官方文档
The high speed external clock signal (HSE) can be generated from two possible clock sources:
• HSE external crystal/ceramic resonator
• HSE user external clock
In this mode, an external clock source must be provided. It can have a frequency of up to
50 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See(高阻态可做开路理解) Figure 12.
External crystal/ceramic resonator (HSE crystal)
The 3 to 25 MHz external oscillator has the advantage of producing a very accurate rate on the main clock.
The associated hardware configuration is shown in Figure 12. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR).
The HSE crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR).
HSI clock
The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input.
解释：HSI时钟信号由内部8MHz的RC振荡器产生，可以直接作为系统时钟(SYSCLK)或在2分频后作为PLL输入时钟。
PLLs
The main PLL provides a frequency multiplier starting from one of the following clock sources:
• HSI clock divided by 2
• HSE or PLL2 clock through a configurable divider
Refer to Figure 11 and Clock control register (RCC_CR).
LSE clock
The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
LSE晶体是一个32.768 kHz低速外部晶体或陶瓷谐振器。 它具有为实时时钟外设（RTC）提供低功耗，高精度时钟源的优势，以实现时钟/日历或其他计时功能。
In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left
Hi-Z.
在这种模式下，必须提供一个外部时钟源。 它可以具有高达1 MHz的频率。 您可以通过将备份域控制寄存器（RCC_BDCR）中的LSEBYP和LSEON位置1来选择此模式。 占空比约为50％的外部时钟信号（正方形，正弦波或三角形）必须驱动OSC32_IN引脚，而OSC32_OUT引脚应保持为Hi-Z(悬空/高阻态)
LSI clock
The LSI RC acts as an low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 40 kHz (between 30 kHz and 60 kHz).
LSI RC充当低功耗时钟源，可为独立看门狗（IWDG）和自动唤醒单元（AWU）保持在“停止”和“待机”模式下运行。 时钟频率约为40 kHz（介于30 kHz和60 kHz之间，因为内部的时钟源一般情况是不够稳定）。
Clock security system (CSS)
STM32内部的一个时钟安全检测系统，一旦检测到HSE时钟故障，则就会切换到内部RC振荡器作为时钟信号输入。
官方文档解释如下：
Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
a failure is detected on the HSE clock, the HSE Oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations.
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock directly or through PLL2, and the PLL clock is used as system clock),a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the external HSE oscillator.If the HSE oscillator clock (divided or not) is the clock entry of the PLL (directly or through PLL2) used as system clock when the failure occurs, the PLL is disabled too.
解释：
时钟安全系统可以通过软件激活。在这种情况下，时钟检测器在HSE振荡器启动延迟后启用，并在该振荡器停止时禁用。
在HSE时钟上检测到故障，HSE振荡器被自动禁用，时钟故障事件被发送到TIM1 Advanced控制计时器的中断输入，并产生中断来通知软件该故障（时钟安全系统中断CSSI ），允许MCU执行救援操作。
如果将HSE振荡器直接或间接用作系统时钟（间接表示：直接或通过PLL2用作PLL输入时钟，而PLL时钟用作系统时钟），则检测到的故障会导致系统时钟切换连接到HSI振荡器，并禁用外部HSE振荡器。如果发生故障时，HSE振荡器时钟（分频或非分频）是用作系统时钟的PLL的时钟输入（直接或通过PLL2），则PLL也被禁用。
Clock-out capability
微控制器时钟输出（MCO）功能允许将时钟输出到外部MCO引脚。
The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 8 clock signals can be selected as the MCO clock.
• SYSCLK
• HSI
• HSE
• PLL clock divided by 2 selected
• PLL2 clock selected
• PLL3 clock divided by 2 selected
• XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
• PLL3 clock selected (for Ethernet)
The selected clock to output onto MCO must not exceed 50 MHz (the maximum I/O speed). The selection is controlled bythe MCO[3:0] bits of the Clock configuration register(RCC_CFGR).
Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.
如果通过硬件选项或软件访问来启动独立看门狗（IWDG），则LSI振荡器被强制打开且无法禁用。 在对LSI振荡器进行温度调节后，将时钟提供给IWDG。
所有外设时钟均来自系统时钟（SYSCLK），但以下情况除外：
1.The USB OTG FS 48 MHz clock which is derived from the PLL VCO clock (2 ×PLLCLK), followed by a programmable prescaler (divide by 3 or 2). This selection is made through the OTGFSPRE bit in the RCC_CFGR register. For proper USB OTG FS
operation, the PLL should be configured to output 72 MHz or 48 MHz.
2.The Flash memory programming interface clock (FLITFCLK) is always the HSI clock(始终来自于HIS时钟)
3.The I2S2 and I2S3 clocks which can be derived from the system clock (SYSCLK) or the PLL3 VCO clock (2 × PLL3CLK). This selection is made through the I2SxSRC bit in the RCC_CFGR2 register. For more information on PLL3 and how to configure the I2S clock to achieve high-quality audio performance, please refer to Section 25.4.3: Clock generator.
I2S全称Inter-IC Sound, Integrated Interchip Sound，或简写IIS，是飞利浦在1986年定义（1996年修订）的数字音频传输标准，用于数字音频数据在系统内部器件之间传输，例如编解码器CODEC、DSP、数字输入/输出接口、ADC、DAC和数字滤波器等。除了都是由飞利浦定义外，I2S和I2C没有任何关系。
4.When the Ethernet is used, the AHB clock frequency must be at least 25 MHz.
