完成课本例题6.11、6.12，进行综合和仿真（功能仿真），查看综合和仿真结果，整理入实验报告。
6.11
module shiyan21(in,clk,out1,out2);
input clk,in;
output out1,out2;
reg out1,out2;
always @(posedge clk)
begin
out1<=in;
out2<=out1;
end
endmodule
`timescale 1ns/1ns
module test();
reg in,clk;
wire out1,out2;
shiyan21 U1(in,clk,out1,out2);
always #10 clk=~clk;
initial
begin clk =0;in=0;
#10 in=1;
#20 in=0;
#10 in=1;
#20 in=0;
#10 in=1;
#20 in=0;
#10 in=1;
#20 in=0;
#10 in=1;
#20 in=0;
#10 in=1;
#20 in=0;
#200 $finish;
end
endmodule
6.12
module shiyan21(in,clk,out1,out2);
input clk,in;
output out1,out2;
reg out1,out2;
always @(posedge clk)
begin
out1=in;
out2=out1;
end
endmodule
`timescale 1ns/1ns
module test();
reg in,clk;
wire out1,out2;
shiyan21 U1(in,clk,out1,out2);
always #10 clk=~clk;
initial
begin clk =0;in=0;
#10 in=1;
#20 in=0;
#10 in=1;
#20 in=0;
#10 in=1;
#20 in=0;
#10 in=1;
#20 in=0;
#10 in=1;
#20 in=0;
#10 in=1;
#20 in=0;
#200 $finish;
end
endmodule
用Verilog语言设计一个类似74138的译码器电路，进行综合和仿真（功能仿真），查看综合和仿真结果，整理入实验报告。
module shiyan22(in,out);
input[2:0] in;
output out;
reg [7:0] out;
always @(*)
begin
case (in)
3'b000: out=8'b11111110;
3'b001: out=8'b11111101;
3'b010: out=8'b11111011;
3'b011: out=8'b11110111;
3'b100: out=8'b11101111;
3'b101: out=8'b11011111;
3'b110: out=8'b10111111;
3'b111: out=8'b01111111;
default: ;
endcase
end
endmodule
`timescale 1ns/1ns
module test();
reg[2:0] in;
wire[7:0] out;
shiyan22 U1(in,out);
initial
begin
#10 in=3'b000;
#10 in=3'b001;
#10 in=3'b010;
#10 in=3'b011;
#10 in=3'b100;
#10 in=3'b101;
#10 in=3'b110;
#10 in=3'b111;
#200 $finish;
end
endmodule
