最近项目需要在调试STM32时遇到外部晶振时钟不稳定，查看RCC_CR寄存器的第17位始终处于0，表示外部晶振始终处于不稳定状态：
当HSE开启时，如果HSERDY一直处于0时，则芯片会启动内部16Mhz晶振,但是此时PLL分频无效，整个系统降到了16Mhz，无法忍受，立刻启动内部时钟源HSI为系统时钟， 同时通过配置PLL，将系统时钟配置到168Mhz,
由于系统设置时钟源是在系统起来厚，main函数之前设置的，在SetSysClock（），首先需要自己设置HSI为系统时钟源，代码如下：
/*** @brief Configures HSI as the System clock source**/ void HSI_SetSysClock(){__IO uint32_t HSIStartUpStatus = 0;RCC_DeInit();//set HSIRCC_HSICmd(ENABLE);HSIStartUpStatus = RCC->CR & RCC_CR_HSIRDY;if (HSIStartUpStatus == RCC_CR_HSIRDY){ /* Select regulator voltage output Scale 1 mode */RCC->APB1ENR |= RCC_APB1ENR_PWREN;PWR->CR |= PWR_CR_VOS;// HCLK = SYSCLK / 1RCC_HCLKConfig(RCC_SYSCLK_Div1);/* HCLK = SYSCLK / 1*/RCC->CFGR |= RCC_CFGR_HPRE_DIV1;#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx) /* PCLK2 = HCLK / 2*/RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;/* PCLK1 = HCLK / 4*/RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F412xG || STM32F446xx || STM32F469_479xx */#if defined(STM32F401xx) || defined(STM32F413_423xx)/* PCLK2 = HCLK / 1*/RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;/* PCLK1 = HCLK / 2*/RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;#endif /* STM32F401xx || STM32F413_423xx */#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx) /* Configure the main PLL */RCC->PLLCFGR = HSI_PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |(RCC_PLLCFGR_PLLSRC_HSI) | (PLL_Q << 24);#endif /* STM32F40_41xxx || STM32F401xx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)/* Configure the main PLL */RCC->PLLCFGR = HSI_PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |(RCC_PLLCFGR_PLLSRC_HSI) | (PLL_Q << 24) | (PLL_R << 28);#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx *//* Enable the main PLL */RCC->CR |= RCC_CR_PLLON;/* Wait till the main PLL is ready */while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) {}#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)/* Enable the Over-drive to extend the clock frequency to 180 Mhz */PWR->CR |= PWR_CR_ODEN;while((PWR->CSR & PWR_CSR_ODRDY) == 0){}PWR->CR |= PWR_CR_ODSWEN;while((PWR->CSR & PWR_CSR_ODSWRDY) == 0){}/* Configure Flash prefetch, Instruction cache, Data cache and wait state */FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */#if defined(STM32F40_41xxx) || defined(STM32F412xG) /* Configure Flash prefetch, Instruction cache, Data cache and wait state */FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;#endif /* STM32F40_41xxx || STM32F412xG */#if defined(STM32F413_423xx) /* Configure Flash prefetch, Instruction cache, Data cache and wait state */FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;#endif /* STM32F413_423xx */#if defined(STM32F401xx)/* Configure Flash prefetch, Instruction cache, Data cache and wait state */FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;#endif /* STM32F401xx *//* Select the main PLL as system clock source */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));RCC->CFGR |= RCC_CFGR_SW_PLL;/* Wait till the main PLL is used as system clock source */while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);{}}}
将上述代码添加到，设置外部时钟源失败异常处理流程SetSysClock（）函数中：
系统恢复如初，系统时钟源恢复到168Mhz,很happy
