格雷码和二进制码转换的Verilog实现
1. 二进制码转换为格雷码:
转换原则:格雷码最高位gray[N]等于二进制码最高位gray[N],格雷码第n位等于二进制码第(n+1)位异或二进制码第n位,n∈[0,N-1],即:gray[N] = binary[N]gray[n] = binary[n+1] ^ binary[n], 其中n∈[0,N-1]
二进制码转换为格雷码的verilog模块实现:
`timescale 1ns/1psmodule bin2gray#(parameter W = 8//位宽)(input [W-1 : 0] binary_code ,//二进制码output [W-1 : 0] gray_code //格雷码);parameter N = W-1 ;//最高位//gray_code[N]assign gray_code[N] = binary_code[N];//gray_code[N-1 : 0]generategenvar i;for(i = 0; i < N; i = i + 1) beginassign gray_code[i] = binary_code[i+1] ^ binary_code[i];endendgenerateendmodule
仿真代码:
`timescale 1ns/1psmodule tb_bin2gray;reg [7:0]binary_code;wire [7:0]gray_code ;//---integer i;//---------------------------------bin2gray#(.W(8)//位宽)bin2gray_inst(.binary_code(binary_code),.gray_code (gray_code ));initial beginfor(i = 0; i < 256; i = i + 1) beginbinary_code = #10 i;end#200;for(i = 0; i < 256; i = i + 1) beginbinary_code = #10 ({$random} % 256);endendendmodule
2. 格雷码转换为二进制码:
转换原则:二进制码最高位bin[N]等于格雷码最高位gray[N],二进制码第n位等于二进制码(n+1)位异或格雷码第n位,n∈[0,N-1],即:binary[N] = gray[N]binary[n] = binary[n+1] ^ gray[n], 其中n∈[0,N-1]
格雷码转换为二进制码的verilog模块实现:
`timescale 1ns/1psmodule gray2bin#(parameter W = 8//位宽)(input [W-1 : 0] gray_code ,//二进制码output [W-1 : 0] binary_code //格雷码);parameter N = W-1 ;//最高位//binary_code[N]assign binary_code[N] = gray_code[N];//binary_code[N-1 : 0]generategenvar i;for(i = 0; i < N; i = i + 1) beginassign binary_code[i] = binary_code[i+1] ^ gray_code[i];endendgenerateendmodule
仿真代码:
`timescale 1ns/1psmodule tb_gray2bin;reg[7:0] gray_code ;wire [7:0] binary_code;//---integer i;gray2bin#(.W(8) //位宽)gray2bin_inst(.gray_code (gray_code ), .binary_code(binary_code) );initial beginfor(i = 0; i < 256; i = i + 1) begingray_code = #10 i;endendendmodule